Information for developers

RDNA4.0 Architecture

https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf

Blackwell Architecture

https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf

https://developer.nvidia.com/blog/cuda-toolkit-12-8-delivers-nvidia-blackwell-support/

https://docs.nvidia.com/cuda/cuda-toolkit-release-notes/index.html#deprecated-or-dropped-features

https://nvdam.widen.net/s/xqt56dflgh/nvidia-blackwell-architecture-technical-brief

In the last technical brief, the tensor cores are FP64 in GB200 superchip 90TeraFLOPS rtx5000 series.

The next generation of rtx 5000, the rtx6000,

https://www.techpowerup.com/gpu-specs/rtx-pro-6000-blackwell.c4272


FP16 (half)
126.0 TFLOPS (1:1)

FP32 (float)
126.0 TFLOPS

FP64 (double)
1.968 TFLOPS (1:64)